14 Transistors CNTFET and CMOS Full Adder Cell for Modified GDI Technique
Priyanka Tyagi1, S.K Singh2, Piyush Dua3

1Priyanka*, Department of ECE, Research Scholar, AKTU, Lucknow, U.P.
2Dr. S.K. Singh, Department of ECE, ABES Enginnering College, Ghaziabad, U.P.
3Dr Piyush Dua, Department of Engineering College of Applied Sciences, Sohar, Oman.

Manuscript received on September 16, 2019. | Revised Manuscript received on 25 September, 2019. | Manuscript published on October 10, 2019. | PP: 842-845 | Volume-8 Issue-12, October 2019. | Retrieval Number: L32331081219/2019©BEIESP | DOI: 10.35940/ijitee.L3233.1081219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Adder Is Basic Unit For Any Digital System, Dsp And Microprocessor. The Main Issue In Design High Speed Full Adder Cell With The Low Power Dissipation. As We Know Cmos Technology Used For Vlsi Designing Cmos Has Many Drawbacks As High Power Short Channel Effect Etc. Then Cntfet (Carbon Nanotube Field Effect Transistor) Has Been Developed Which Has Same Structure As Cmos. The Difference Between Structure Of Cmos And Cntfet Is Their Channel. In Cntfet Channel Is Replaced By Carbon Nanotube. In This Paper We Compare Full Adder Circuit Using Cntfet With Gdi Technique And Cmos Implementation Of Adder Which Gdi Technique. Gdi Technique Is Used For Speed And Power Optimization In Digital Circuit. This Can Also Reduce The Count Of Transistor Which Affects The Size Of Device.
Keywords: CNTFET, CMOS, GDI , PTL , C2MOS ,MGDI, Delay, PDP
Scope of the Article: Data Mining Methods, Techniques, and Tools