Design of Hybrid LUT/MUX FPGA Logic Architecture for size Reduction and Performance Improvement in FPGA
1V.Aruna, M.Tech (Vlsi And Es) Godavari Institute Of Engineering And Technology, Rajahmundry, A. P. India.
2Ch.Srigiri, Asst.Professor, Dept. Of Electronics & Communication Engg In Godavari Institute Of Engineering And Technology, Rajahmundry, A. P. India.
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 4883-4889 | Volume-8 Issue-12, October 2019. | Retrieval Number: L34911081219/2019©BEIESP | DOI: 10.35940/ijitee.L3491.1081219
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Abstract: Hybrid configurable logic block architectures for field-programmable gate arrays that contain a blend of LUT’s and solidified multiplexers that are assessed towards the objective of higher rationale thickness and diminished region. Innovation mapping advancements that focus on the proposed models are likewise perform inside Xilinx programming. Both for complex rationale square and steering territory while keeping up mapping profundity, the named engineering of this paper examine the rationale size, region and power utilization utilizing Xilinx 14.5.
Keywords: FPGA, CLB’s, and Look up Tables, Multiplexers, and Fracturable Architectures.
Scope of the Article: Network Architectures