A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration
Rajesh A1, Jameer Basha SK2, Francis Xavier3, Hari Babu S4
1Mr. Rajesh A, Assistant Professor, Department of EECE, GITAM Hyderabad, India.
2Mr. Jameer Basha SK, Assistant Professor, Department of EECE, GITAM Hyderabad, India.
3Mr. Francis Xavier, Assistant Professor, Department of EECE, GITAM Hyderabad, India.
4Mr. Hari Babu S, Assistant Professor, Department of EECE, GITAM Hyderabad, India.
Manuscript received on September 14, 2020. | Revised Manuscript received on September 23, 2020. | Manuscript published on October 10, 2020. | PP: 217-220 | Volume-9 Issue-12, October 2020 | Retrieval Number: 100.1/ijitee.L79851091220 | DOI: 10.35940/ijitee.L7985.1091220
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.
Keywords: FPGA, BIST, CLB testing, Complentary gates, Look up table, Fault coverage.
Scope of the Article: FPGAs