Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique
Challa Lakshmi jyothi1, S Hanumantha Rao2

1Lakshmi Jyothi Challa, B. Tech in ECE from JNTUK. Pursuing M. Tech VLSI Design in Shri Vishnu Engineering College for Women, Bhimavaram, India.
2S Hanumantha Rao, Assistant Professor in Electronics& Communication Engineering College for Women, Bhimavaram, India.
Manuscript received on September 23, 2020. | Revised Manuscript received on October 02, 2020. | Manuscript published on October 10, 2020. | PP: 323-328 | Volume-9 Issue-12, October 2020 | Retrieval Number: 100.1/ijitee.L79921091220 | DOI: 10.35940/ijitee.L7992.1091220
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Abstract: VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR-XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR-XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR-XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR-XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model. 
Keywords: Full adder(FA), GDI, VLSI, Full-Swing, CMOS.