Surface Potential Modelling Based Performance Analysis of Gate Engineered Trapezoidal Trigate Tunnel FET
Aadil Tahir Shora1, Mujtaba Yousuf Kathjoo2, Masrat Maqbool Khan3
1Dr. Aadil T. Shora, Faculty, Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar (Jammu and Kashmir), India
2Mujtaba Y. Kathjoo, Scholar, Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar (Jammu and Kashmir), India
3Masrat M. Khan, Student, Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar (Jammu and Kashmir), India
Manuscript received on 12 October 2022 | Revised Manuscript received on 19 October 2022 | Manuscript Accepted on 15 November 2022 | Manuscript published on 30 November 2022 | PP: 33-37 | Volume-11 Issue-12, November 2022 | Retrieval Number: 100.1/ijitee.L932111111222 | DOI: 10.35940/ijitee.L9321.11111222
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a three dimensional (3-D) analytical model of surface potential has been derived for gate engineered trapezoidal trigate Tunnel Field Effect Transistor (TFET). The model has been obtained by assuming parabolic approximation of the potential profile and solving 3-D Poisson equation using appropriate boundary conditions. The device considered in this work is silicon based TFET with gate composed of two materials with different work functions. The low work-function material is placed close to source and drain region while high work-function material is placed in between them. This will result in enhancing the tunneling in the source/channel interface region while reducing the electric field in the drain region. Trigate devices have been found to enhance the device performance at nanoscale, however, Trigate device fabricated by Intel have been found to have trapezoidal shape rather than expected rectangular shape. In this work, we have included the effect of different inclination angles of sides on the device performance. The model has been verified by comparing the results with the simulation results obtained in ATLAS software.
Keywords: Tunnel FET; Dual material Gate; Trigate TFET, Trapezoidal FET, Silicon-On-Insulator (SOI) Transistor.
Scope of the Article: Dual Material Gate