Design and Analysis of Low off Set High Speed Low Power 1Kb SRAM Memory
Vishvender Singh1, Gunjan Agarwal2, Mukesh Sharma3

1Vishvender, Department of ECE, BSAITM, Faridabad (Haryana),India.
2Gunjan Agrwal, Assistant Professor, Department of ECE, BSAITM, Faridabad (Haryana),India.
3Mr. Mukesh Sharma, Assistant Professor, Department of ECE, BSAITM, Faridabad (Haryana),India.
Manuscript received on 12 June 2014 | Revised Manuscript received on 19 June 2014 | Manuscript Published on 30 June 2014 | PP: 57-61 | Volume-4 Issue-1, June 2014 | Retrieval Number: A1707064114/14©BEIESP
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Abstract: This paper we present the design and analysis of 1Kb Static Random Access Memory (SRAM) at 180nm technology and main focusing on optimizing power consumption and delay factors are improved by varying the size of transistor used in Sense Amplifier. The present 1kb SRAM can be divided into main three block sense amplifier, basic cell and precharged circuit. Present 1kb SRAM design input decoupled sense amplifier. Presented Sense amplifier CMOS schematic is design tanner EDA S-edit, Simulate T-spice and 0.18µm technology.
Keywords: Sense Amplifier, Driver Transistor, Access Transistor, Load Transistor.

Scope of the Article: Low-power design