A Novel 1-Bit Full Adder Design Using DCVSL XOR/XNOR Gate and Pass Transistor Multiplexers
P. Divakara Varma1, R.Ramana Reddy2
1P. Divakara Varma, Department of Electronics and Communication Engineering, MVGR College of Engineering, Vizianagaram (A.P), India.
2Dr. R. Ramana Reddy, Department of Electronics and Communication Engineering, MVGR College of Engineering, Vizianagaram (A.P), India.
Manuscript received on 12 March 2013 | Revised Manuscript received on 21 March 2013 | Manuscript Published on 30 March 2013 | PP: 142-146 | Volume-2 Issue-4, March 2013 | Retrieval Number: D0556032413/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adders are the basic building blocks in digital computer systems. Arithmetic operations are widely used in most digital computer systems. Addition is a fundamental arithmetic operation and is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding another xor gate and can be used for division. Therefore, 1-bit Full Adder cell is the most important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell. There is always a trade-off between speed and power dissipation in VLSI Design. To achieve high speeds, high drivability hybrid-DCVSL design methodologies are used to build adder cell in this work. Static CMOS, DCVSL adders are compared with hybrid XOR and XNOR based hybrid adder cell for delay, power dissipation and number of transistors utilized. The hybrid adder is designed using DCVSL gates because these can produce both complementary and true outputs using single gate architecture. The multiplexers in the design are based on the pass transistor logic (PTL) because these are simple to construct and occupies less chip area per component.
Keywords: DCVSL, Multiplexer, PTL, XOR/XNOR.
Scope of the Article: Low-power design