New Algorithm for Dht and Its Verilog Implementation
Anamika Jain1, Neeta Pandey2

1Anamika Jain*, Department of ECE, Maharaja Agrasen Institute of Technology(MAIT) affiliated to GGSIP University, Delhi, India.
2Prof. Neeta Pandey, Department of ECE, Delhi Technological University(DTU) Delhi University, Delhi, India.
Manuscript received on January 10, 2020. | Revised Manuscript received on January 21, 2020. | Manuscript published on February 10, 2020. | PP: 2908-2912 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1910029420/2020©BEIESP | DOI: 10.35940/ijitee.D1910.029420
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Abstract: This paper presents a new algorithm for computing Discrete Hartley Transform (DHT) (type-2) of N with N=4r , where r>1.Paper also suggest VLSI architecture for the implementation of the newly developed algorithm. The computation of DHT using this algorithm is simple and requires less arithmetic operations compared with the general method for finding DHT. Also the suggested VLSI structure for the algorithm is regular and less complicated in terms of hardware requirement. Parallel processing of the algorithm make the processing further fast. 
Keywords: Discrete Hartley Transforms, Recursive Structure, Parallel Processing.
Scope of the Article: Parallel and Distributed Algorithms