Design of High Speed CODEC for On Chip Cross Talk Avoidance
Ganesh Kumar B1, R.P.Das2, K.V.Ramana Rao3
1GB.Ganesh Kumar, ECE Department, JNTUK University, Pydah College of Engineering and Technology, Visakhapatnam, India.
2R.P.Das, ECE Department , JNTUK University, Pydah College of Engineering and Technology , Visakhapatnam, India.
3K.V.Ramana Rao, ECE Department , JNTUK University, Pydah College of Engineering and Technology , Visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 05, 2012. | Manuscript published on October 10, 2012. | PP: 7-9 | Volume-1 Issue-5 October 2012. | Retrieval Number: E0275091512/2012©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The cross talk is dependent on the data transition patterns on the bus, patterns can be classified based on the severity of the crosstalk they impose on the bus. The general idea behind techniques that improve on-chip bus speed is to remove undesirable patterns that are associated with certain classes of crosstalk. Different schemes incur different area overheads since they requires additional wires, spacing between wires or both. We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists between the data wordsand code words. Our proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed. The design was implemented on Xilinx Xc3S200 fpga and the total power consumed by the device was estimated as 0.041W.
Keywords: CODEC, FPF-CAC, pruning,shielding.