BIST based can Bus Control System Implemented into FPGA
Amit Kumar Bhadrawat1, Sourabh Sharma2

1Amit Kumar Bhadrawat, M.Tech Student, Trinity Institute of Technology and Research, Bhopal (M.P), India.
2Sourabh Sharma, Assistant Professor, Department of EC, Trinity Institute of Technology and Research, Bhopal (M.P), India.
Manuscript received on 17 October 2014 | Revised Manuscript received on 24 October 2014 | Manuscript Published on 30 October 2014 | PP: 29-33 | Volume-4 Issue-5, October 2014 | Retrieval Number: E1821104514/14©BEIESP
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Abstract: Electronics components in many application required maximum level of fault tolerance and high reliability . Application like avionic, railway ,deep space mission can serve as an example of these applications. In these applications, electronics components are exhibited to the environment conditions, from among them especially cosmic radiation can have an undesired and destructive effect. In this paper,the design and implementation of BIST based CAN bus control system into FPGA is described. The bus control system uses CAN Aerospace application protocol .the fault tolerant features of the developed system are improved by BIST architecture. Then, experiments With SEU injection into the FPGA configuration memory with both non-TMR and BIST architectures are described, the results presented and evaluated.
Keywords: CAN Bus, BIST, Fault, Fault Tolerant, FPGA, TMR.

Scope of the Article: Signal Control System & Processing