Design of 12-Bit SAR ADC using Split Capacitor Based DAC Architecture at 45nm CMOS Technology
Naveen I .G1, Savita sonoli2

1Mr.Naveen I .G, working as Asst. Professor, E&CE Dept., Sir MVIT, Bengaluru
Dr. Savita Sonoli, Vice Principal & Head, E&CE Dept., RYMEC, Bellary, Karnataka, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 2530-2535 | Volume-8 Issue-12, October 2019. | Retrieval Number: J95130881019/2019©BEIESP | DOI: 10.35940/ijitee.J9513.1081219
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Abstract: Nowadays, there is an increasing demand for Successive Approximation Register (SAR) based Analog to Digital Converter (ADC) in long battery applications like medical application, Sensors and many more. In this paper DAC circuit is designed using multiple capacitor and Multiple MUX for switching. A split based capacitor is used for boosting the speed of the architecture. In split based DAC no common mode voltage required and dynamic offset can be removed as well. In this work, 12-Bit DAC and encoder is designed using 2 Transistor MUX and 18 Transistor Full adders (12B-2TM-18TFA). 2T and 18T is used to design the MUX and FA. This entire architecture is implemented in Cadence Virtuoso 45nm CMOS technology. Simultaneously, 10B-12TM-36TFA architecture also implemented in this paper. The performance parameters like area, power, and delay, current is evaluated for both architectures. Result showed that 12B-2TM-18TFA architecture consumed less area, less power, less delay, and less current compared to 10B-12TM-36TFA.
Keywords: Analog to Digital Convertor, Digital Analog Converter, Successive Approximation Register, 18T MUX, 2T MUX.
Scope of the Article: Service Oriented Architectures