Implementation of Phase Frequency Detector in Phase locked loop using Preset ablemodified TSPC D flip-flop
S.Praseetha1, Benedict Tephila M2, Anusuya S3
1Mrs.S.Praseetha*, Department of ECE, Sri Krishna College of Engineering & Technology, Coimbatore, India.
2Ms.Benedict Tephila M, Department of ECE, Sri Krishna College of Engineering & Technology, Coimbatore, India.
3Ms.Anusuya S, Department of ECE, Ramakrishna college of Engineering and technology , Trichy, , India
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 977-980 | Volume-8 Issue-12, October 2019. | Retrieval Number: J98280881019/2019©BEIESP | DOI: 10.35940/ijitee.J9828.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.
Keywords: DFF, PFD, PLL, MTSPC D flipflop, TSPC D flip-flop.
Scope of the Article: Frequency Selective Surface