Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA
Keshav Kumar1, Bishwajeet Pandey2, Amit Kant Pandit3, Yousef A. Baker El-Ebiary4, Salameh A. Mjlae5, Samer Bamansoor6

1Keshav Kumar, Gyancity Research Consultancy Pvt Ltd, Motihari (Bihar), India. 

2Bishwajeet Pandey, Gyancity Research Consultancy Pvt Ltd, Motihari (Bihar), India. 

3Amit Kant Pandit, Shri Mata Vaishno Devi University (SMVDU), Katra, Jammu and Kashmir, India. 

4Yousef A. Baker El-Ebiary, Faculty of Informatics and Computing, UniSZA, Malaysia. 

5Salameh A. Mjlae, Balqa Applied University, Salt, Jordan. 

6Samer Bamansoor, Al-Madinah International University, Kuala Lumpur, Malaysia. 

Manuscript received on 06 December 2019 | Revised Manuscript received on 20 December 2019 | Manuscript Published on 31 December 2019 | PP: 27-30 | Volume-8 Issue-12S2 October 2019 | Retrieval Number: L100610812S219/2019©BEIESP | DOI: 10.35940/ijitee.L1006.10812S219

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Abstract: In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more power-efficient as voltage supply increases.

Keywords: Spartan-3, Spartan-6, Power, Voltage, Field-Programmable Gate Array (FPGA), Universal Asynchronous Receiver Transmitter (UART).
Scope of the Article: Low-power design