Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design
Sana1, Anum Khan2, Subodh Wairya3

1Sana*, Electronics and Communication Department, Institute of Engineering & Technology, Lucknow, India.
2Anum Khan, Electronics and Communication Department, Institute of Engineering & Technology, Lucknow, India.
3Subodh Wairya, Electronics and Communication Department, Institute of Engineering & Technology, Lucknow, India.
Manuscript received on September 20, 2020. | Revised Manuscript received on September 25, 2020. | Manuscript published on October 10, 2020. | PP: 348-354 | Volume-9 Issue-12, October 2020 | Retrieval Number: 100.1/ijitee.L80241091220 | DOI: 10.35940/ijitee.L8024.1091220
Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU. Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chainsstructure. In this paper two new hybrid full adders have been proposed with an aim to achieve low PDP. Further the paper proposesripple carry adder (RCA) in chainstructure using triplet design approach to improve the driving strength. Fivedifferent hybrid full adders topologies have been implementedto build 4-bit RCA adder in regular and triplet logic design and PDP improvement is obtained in triplet design approach. All the simulations are done on 45nm technology and performance analysis done over the voltage range 0.6 V to 1.2V in Cadence Virtuoso simulation software. Simulation results are obtained to show that delay and PDP has improved in triplet designing and the proposed hybrid adders represents least PDP among other implemented reference circuits. 
Keywords: Hybrid full adder, Power delay product, Ripple carry adder, Triplet design