Volume-1 Issue-4, September 2012 – International Journal of Innovative Technology and Exploring Engineering (IJITEE)

D0257081412

IJITEE Journal — Fri, 29 Oct 2021 05:42:50 +0000

The International Journal of Innovative Technology and Exploring Engineering (IJITEE) has ISSN: 2278-3075 (online), an open-access, peer-reviewed, periodical monthly international journal. This journal is published by Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) in January, February, March, April, May, June, July, August, September, October, November and December.The journal aims to publish high–quality peer–reviewed original articles in the area of Engineering and Technology that covers Computer Science and Engineering, Information Technology, Electrical and Electronics Engineering, Electronics and Telecommunication, Mechanical Engineering, Civil Engineering and all interdisciplinary streams of Engineering and Technology. #Smart Computing and Information Processing #Signal and Speech Processing #Image Processing and Pattern Recognition #WSN#Artificial Intelligence and machine learning #Data mining and warehousing #Data Analytics #Deep learning #Bioinformatics #High Performance computing #Advanced Computer Networking #Cloud Computing #IoT #Parallel Computing on GPU #Human Computer Interactions #Recent Trends in Microelectronics and VLSI Design #Process & Device Technologies #Low-Power Design #Nanometer-Scale Integrated Circuits #Application specific ICs (ASICs) #FPGAs #Nanotechnology #Nano Electronics and Quantum Computing #3. Challenges of Industry and their Solutions, Communications #Advanced Manufacturing Technologies #Artificial Intelligence #Autonomous Robots #Augmented Reality #Big Data Analytics and Business Intelligence #Cyber Physical Systems (CPS) #Digital Clone or Simulation #Industrial Internet of Things (IIoT) #Manufacturing IoT #Plant Cyber Security #Smart Solutions – Wearable Sensors and Smart Glasses #System Integration #Small Batch Manufacturing #Visual Analytics #Virtual Reality #3D Printing # Internet of Things (IoT) #Internet of Things (IoT) & IoE & Edge Computing #Distributed Mobile Applications Utilizing IoT #Security, Privacy and Trust in IoT & IoE #Standards for IoT Applications #Ubiquitous Computing #Block Chain-enabled IoT Device and Data Security and Privacy #Application of WSN in IoT #Cloud Resources Utilization in IoT #Wireless Access Technologies for IoT #Mobile Applications and Services for IoT #Machine/ Deep Learning with IoT & IoE #Smart Sensors and Internet of Things for Smart City #Logic, Functional programming and Microcontrollers for IoT #Sensor Networks, Actuators for Internet of Things #Data Visualization using IoT #IoT Application and Communication Protocol #Big Data Analytics for Social Networking using IoT #IoT Applications for Smart Cities #Emulation and Simulation Methodologies for IoT #IoT Applied for Digital Contents #Microwaves and Photonics #Microwave filter #Micro Strip antenna #Microwave Link design #Microwave oscillator #Frequency selective surface #Microwave Antenna #Microwave Photonics #Radio over Fibre #Optical Communication, #Optical Oscillator #Optical Link Design #Optical Phase Lock Loop #Optical Devices #Computation Intelligence and Analytics #Soft Computing #Advance Ubiquitous Computing #Parallel Computing #Distributed Computing #Machine Learning #Information Retrieval #Expert Systems #Data Mining #Text Mining #Data Warehousing #Predictive Analysis #Data Management #Big Data Analytics #Big Data Security #Energy Harvesting and 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Impacts of Facts Technology-A State of Art Review
Abhishek Gandhar¹, Balwinder Singh², Rintu Khanna³
¹Abhishek Gandhar, Ph.D, Research Scholar, PEC University of Technology, Chandigarh, India.
²Dr. Balwinder Singh, Associate Professor, PEC University of Technology, Chandigarh, India.
³Dr. Rintu Khanna, Assistant Professor, PEC University of Technology, Chandigarh, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 28-31 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0257081412/2012©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: FACTS (Flexible AC Transmission Systems) means a whole family of controllers and devices for increase the use and flexibility of power systems. These controllers are installed in many places and improving the capabilities of different power systems.. This paper presents a review on the research and developments in the area of FACTS controllers and their contributions. This paper will treat benefits of FACTS devices installed in power systems such as increment in power transmission capability and a reduction in transmission losses. And improved transient and dynamic stability, This paper also includes the main barriers of voltage instability and power transmission structure. Authors strongly believe that this survey article will be very much useful to the researchers for finding out the relevant references in the field of voltage stability improvement by using FACTS controllers.
Keywords: FACTS, SVC, STATCOM, UPFC.

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D0268081412

IJITEE Journal — Fri, 29 Oct 2021 05:08:44 +0000

Distributed Estimation in Wireless Sensor Networks with Heterogeneous Sensors
Zhenxing Luo
Zhenxing Luo, Department of Electrical and Computer Engineering, the University of Alabama at Birmingham, AL, USA.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 79-82 | Volume-1 Issue-4, September 2012. | Retrieval Number:D0268081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, a robust distributed estimation method in wireless sensor networks (WSNs) with heterogeneous sensors is presented. Particularly, a single parameter is estimated based on decisions from heterogeneous sensors, which have different signal gains. The sensor gains follow uniform distributions. Using the distributions of sensor gains, we calculated the probability density function of the signal received by sensors. Then, the overall likelihood function for a given decision vector is derived and a maximum likelihood estimation (MLE) method is used to estimate the unknown parameter. To evaluate estimation performance, the Cramer-Rao lower bound (CRLB) is also derived. Simulation results showed that if the range of sensor gains was narrow, the RMS errors were close to CRLB. If the range of sensor gains was wide, the RMS errors deviated from CRLB.
Keywords: Distributed Estimation, Maximum Lestimation, Wireless Sensor Networks.

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D0239081412

IJITEE Journal — Fri, 29 Oct 2021 05:04:45 +0000

Analysis of Ambient Noise Level and its Impact on the Capacity and Coverage of CDMA System
Ohaneme C.O.¹, Idigo V.E.², Oguejiofor O.S.³, Nnebe S.U.⁴
¹Dr. C.O. Ohaneme, Department of Electronic and Computer Engineering Nnamdi Azikiwe University, Awka, Nigeria.
²Dr. V.E. Idigo, Department of Electronic and Computer Engineering, Nnamdi Azikiwe University, Awka, Nigeria.
³S.O. Oguejiofor, Department of Electronic and Computer Engineering, Nnamdi Azikiwe University, Awka, Nigeria.
⁴S.U. Nnebe, Department of Electronic and Computer Engineering, Nnamdi Azikiwe University, Awka, Nigeria.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 72-78 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0239081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Communication services have been the most intriguing things to network users in recent times. Hence there is the need to provide adequate communication facilities such as robust technologies in order to sustain the number of subscribers that are connected to wireless network daily. Therefore this paper provides the best platform to study the effect of ambient noise on wireless cellular network and how it affects the capacity and coverage of the cellular system. Special consideration is given to the Visafone CDMA network cellular environment of South-East Nigeria for the study from where the received signal levels from base stations are taken at various locations. The system is simulated using Matlab to give the vivid account of the effects of ambient noise within the cellular network and how it can be reduced. The simulation results show that at lower ambient noise, an advantage of a network capacity is achieved.
Keywords: Ambient Noises, Wireless Network, Electromagnetic Waves, Thermal Noise, Reuse Efficiency and Ionosphere.

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D0267081412

IJITEE Journal — Fri, 29 Oct 2021 04:56:30 +0000

Carbon Nanotube Field Effect Transistor: Fabrication of Thin Film of SiO2-Based Micro Cantilevers Dielectric Layer between the Channel and Substrate by Anisotropic Chemical Etching of (100) Single Crystal Si
Kuldeep Niranjan¹, Sanjay Srivastava², Jaikaran Singh³, Mukesh Tiwari⁴
¹Kuldeep Niranjan, M.Tech Scholar (VLSI), SSSIST, Sehore (M.P.), India.
²Dr. Sanjay Srivastava, Professor, Department of Msme, Manit, Bhopal (M.P.), India.
³Prof. Jaikaran Singh, Professor & Head, Depatment of Electronics and Communication, SSSIST, Sehore (M.P.), Inida.
⁴Prof. Mukesh Tiwari, Dean Academic, SSSIST, Sehore (M.P.), Inida.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 67-71 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0267081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The performance of the CNT-FET with variable channel length was modified by using the micro-cantilever, micro-bridge of SiO2. The etching technique was used to prepare the micro cantilever of SiO2 from the Si-substrate. We focus the idea about for the fabrication of the nano-device, in order to reduce the dielectric layer thickness. The channel length of the FET was altered along with the dimension of the substrate. One of the possibilities to reduce the thickness of the dielectric layer is either by etching processes or growing the oxide layer from the substrate through etching process. In this case Laser leaching process was used to reduce the thickness of the substrate. Various electrical properties like gate voltage, drain current, mobility, and device performance have been investigated. A better I-V characteristic was obtained with higher mobility in between the channel and used dielectric layer.
Keywords: Anisotropy, CNT-FET, Lateral growth, Micro-cantilever.

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D0260081412

IJITEE Journal — Fri, 29 Oct 2021 04:48:54 +0000

FPGA Implementation of 64 Point FFT Processor
Vasantha Sudheer N¹, Venu Gopal B²
¹Vasantha Sudheer N, M.Tech Ece Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
²Venu Gopal B, Assoc .Professor, Dept. of Ece, Kaushik College of Engineering, visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 63-66 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0260081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: A power efficient Fast Fourier Transform (FFT) processor for use in the Direction of Arrival (DOA) estimation of a wideband waveform is presented. The target device for implementation is a Xilinx Spartan-3 Xc3s200 Field Programmable Gate Array (FPGA). The FFT processor was developed using the Xilinx ISE in Verilog code. Although the parallel and pipelined architecture uses a large portion of the available FPGA resources, the architecture does yield a high throughput. The total power cosumed by the design is 0.081W.
Keywords: Direction of Arrival (DOA), Fast Fourier Tansform (FFT),FPGA.

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D0259081412

IJITEE Journal — Fri, 29 Oct 2021 04:41:44 +0000

A New Binary Tree Approach of Huffman Code
Asha Latha P¹, Rambabu B²
¹Asha Latha, is pursuing M.Tech(VLSI) in the Department of Ece at Kaushik College of Engineering, Visakhapatnam, (A.P), India.
²B. Rambabu, Assoc Prof, Ece at Kaushik College of Engineering & Technology, Visakhapatnam, (A.P), India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 59-62 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0259081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Lossless compression of a sequence of symbols is important in Information theory as well as today’s IT field. Huffman coding is lossless and is most widely used. However, Huffman coding has some limitations depending on the stream of symbols appearing in a file. In fact, Huffman coding generates a code with very few bits for a symbol that has a very high probability of occurrence and a larger number of bits for a symbol with a low probability of occurrence [1]. In this paper, we present a novel technique that subdivides the original symbol sequence into two or more sub sequences. We then apply Huffman coding on each of the sub sequences. This proposed scheme gives approximately 10-20% better compression in comparison with that of straightforward usage of Huffman coding. The target FPGA deivce for implementing the design is Xilinx Xc3s500E.The devices utilises 9% and 17% of the total flip flops and LUT’s in the FPGA. The total power consumed the device 0.041W.
Keywords: Huffman decoding, Table lookup.

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D0251081412

IJITEE Journal — Fri, 29 Oct 2021 04:34:23 +0000

Image Compression Technique using Two Dimensional Discrete Cosine Transform
S. Rajeswari¹, P. Deepthi², K. V. Ramana Rao³
¹S. Rajeswari, M.Tech Ece, Department, JNTU Kakinada University, Pydah College of Engineering and Tehnology, Visakhapatnam, India.
²P. Deepthi, Asst. Professor ,Dept. of Ece, Pydah College of Engineering & Technology, India.
³K.V. Ramana Rao, Assoc. Professor & Head, Dept. of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 56-59 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0251081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper presents an architecture for the fast computation of the 8×8 two dimensional (2D) Inverse Discrete Cosine Transform. The proposed method is the permanent storage of the Basis Matrices of the 8×8 2D Discrete Cosine Transform (DCT). The sparseness property of the 2D DCT coefficient matrix, the computational time decreases as the number of nonzero coefficients decreases. The proposed structure computes all 64 pixel luminance values of an 8×8 block simultaneously. The design was implemented in Xilinx Xc3s500 board and the design used 23% LUT’s and 33% of the total slices. The total power consumed by the device was 0.081W.
Keywords: 2D IDCT, Image Processing, Sparse Matrices.

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D0250081412

IJITEE Journal — Fri, 29 Oct 2021 04:27:03 +0000

Single Dictionary based Cache Compression and Decompression Algorithm
Prasad Munasa¹, P. Jayanagalakshmi²
¹Prasad Munasa, M.Tech Ece Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
²P. Jayanagalakshmi, Asst. Professor , Dept. of Ece, Kaushik College of Engineering , India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 51-55 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0250081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. All work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. It is not possible to determine whether compression at levels of the memory hierarchy closest to the processor is beneficial without understanding its costs. Furthermore, as we show in this paper, raw compression ratio is not always the most important metric. In this paper, we present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. Apart from that we reduced the proposed algorithm to a register transfer level hardware implementation on Xilinx xc3s500E fpga permitting performance, power consumption, and area estimation. The total power consumption of the device was estimated to be 0.081W.
Keywords: Cache Compression, Pair Matching, Parallel Compression, Hardware Implementation.

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D0249081412

IJITEE Journal — Fri, 29 Oct 2021 04:20:17 +0000

Dynamic Power Suppression Technique in Booth Multipliers
B. Rajani Kumari¹, K. V. Ramana Rao²
¹B.Rajani Kumari, M.Tech ECE Department, JNTU Kakinada University Pydah College of Engineering and Tehnology, Visakhapatnam, India.
²K.V. Ramana Rao, Assoc. Professor & Head, Dept. of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 47-49 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0249081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The SPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction. This paper provides the experience of applying an advanced version of our former spurious power suppression technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the use-less switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement. Adopting a Xilinx Spartan 3 Xc3s200 board the proposed SPST-equipped multiplier dissipates only 0.0121 m W per MHz in H.264 texture coding applications, and obtains a 40% power reduction and the overall utilization of the resources reduced to 26%.
Keywords: Low-power Multiplier, Spurious Power Suppression Technique (SPST).

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D0248081412

IJITEE Journal — Fri, 29 Oct 2021 04:12:14 +0000

A Concurrent Self Repair Scheme for Defects in Random Access Memories
Sandeep Sivvam¹, Solomon Gotham²
¹Sandeep Sivam, M.Tech ECE Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
²Solomon Gotham, Professor & Head, Dept. of ECE, Kaushik College of Engineering , Visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 44-46 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0248081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e.,the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 64-bit RAM with two spare rows and two spare columns. The design is implemented on Xiliinx Spartan3E FPGA and the device used 532 flip-flops out of 3840 available and 439 LUT’s out of 3840 and the number of IO blocks used is 13. Moreover, the time overhead of redundancy analysis is very small. Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Total power utilized by the device was0.041mW. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns.
Keywords: BIRA, REBIRA.

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